An instruction queue is typically a random-access storage array which holds instructions between the time they are fetched from memory and when they are issued to an execution unit. The queue is typically structured as a set of rows, each of which holds one instruction.
In many modern microprocessors, instructions issue from the instruction queue out-of-order, with instruction prioritization managed with pointers to the oldest and newest instructions in the queue. The concept of out-of-order execution is also called “dynamic execution” or “dynamic scheduling”. The queue structure itself may also be called an “instruction buffer”, “re-order buffer”, or “scoreboard”.
In some CPUs, for example, the instruction queue is called a “Re-order Buffer.” There are two buffers, one for ALU instructions and one for memory operations, each containing twenty-eight entries. Instructions remain in a buffer from the time they are fetched until they are retired, and are not removed at issue time. Instructions are inserted into a queue in a round-robin fashion based on the “newest” instruction pointer.
Other instruction queue architectures, sometimes called re-order buffers, appear to hold twenty-four instructions through similar execute and retirement operations.
Other out-of-order issue machines with a 16-entry or larger re-order buffer track the status of each in-flight instruction, and twelve integer and eight floating-point “rename buffers” assign instructions to execution units. Each execution unit has a “reservation station,” that is, an instruction buffer dedicated to an execution unit from which data-ready instructions are issued.